Existing conventional DRAMs do not employ frames for data transfer. Data signals, such as write data, command, and addresses are transmitted in parallel through separate data, command, and address signal busses from a memory controller to one or more semiconductor memory chips (DRAM).
In future DRAM memory systems and memory chips data will be transmitted at very high frequencies. The data transfer will likely be ruled by a protocol with the data bits being organized in frames in accordance with the protocol. After several alignment procedures, for example, a data stream is demultiplexed to a lower frequency and ready for evaluation. Such a novel semiconductor memory chip must include a frame decoder unit to decode the signal frames to: (a) memory relevant commands; (b) system commands; and (c) write data to be intermediately stored in an intermediate data buffer “IDB.” Each frame can contain one or more memory relevant commands. Further, commands dedicated to the same bank can be placed in different frames.